In an electronic device such as a semiconductor element, semiconductor parts such as transistors, resistors and the like are arranged on a substrate. Those parts must be electrically isolated from each other, and hence among them it is necessary to form an area separating them. This area is referred to as an “isolation area”. Hitherto, the isolation area has been generally provided by forming an insulating film selectively on the surface of the semiconductor substrate.
Meanwhile, recently in the field of electronic device technology, the density and the integration degree have been more and more increased. According as the density and the integration degree are becoming higher, it is getting more difficult to form an isolation structure having fineness corresponding to the required integration degree. It is, therefore, desired to provide a new isolation structure satisfying the required fineness. As one of the isolation structures capable of satisfying the requirement, a trench isolation structure is proposed. The trench isolation structure is fabricated by forming fine trenches on a semiconductor substrate and then by filling the trenches with insulating material so as to electrically separate the part positioned on one side from that on the other side of each trench. The structure thus electrically separating the parts can reduce the isolation area, as compared with the conventional insulating film, and accordingly is effective in achieving the integration degree required in these days.
For fabricating the trench isolation structure, a CVD method or a high density plasma CVD method, for example, can be used (see, for example, Patent document 1). However, if the trenches having fineness required in these days, for example, the trenches of 100 nm width or less are filled in according to those methods, some voids are often contained in the filled trenches. These structural defects are liable to deteriorate the physical strength of the substrate and/or to impair the isolation characteristics.
In order to favorably fill the trenches in, it is proposed (for example, in Patent document 1) that a solution of silicon hydroxide was applied on the substrate and then subjected to thermal treatment so as to be converted into silicon dioxide. However, in this method, when the silicon hydroxide is converted into silicon dioxide, the volume shrinkage often caused to form cracks.
For avoiding the cracks, it is also proposed (for example, in Patent documents 1 to 4) to use polysilazane in place of the silicon hydroxide. When the polysilazane is converted into silicon dioxide, its volume shrinkage is less than that of silicon hydroxide. Accordingly, the cracks formed by the volume shrinkage can be avoided. This method comprises the steps of coating a composition containing polysilazane to fill the trenches in, and then treating the coated composition in an oxidizing atmosphere to produce a trench isolation structure made of highly pure and dense silicon dioxide. Since the composition sufficiently penetrates into the trenches, this method has the advantage of forming few voids. However, the present inventors have found that, in producing the trench isolation structure, a siliceous film formed in the above manner is etched so unevenly that the etching rate at the surface is different from that in the trenches. The reason of this is presumed to be as follows. When the polysilazane is converted into silicon dioxide to form the siliceous film, the reaction conditions at the surface are delicately different from those in the trenches. Accordingly, the characteristics of the siliceous film in the trenches are different from those out of the trenches, and also they depend on the depth in the trenches. As a result, the siliceous film is inhomogeneous in terms of the etching rate. This problem is remarkable when the film is subjected to a low temperature treatment, which is often required by restrictions on the device design and/or on the process design. For example, the etching rate is particularly large at positions in trenches having high aspect ratios.    [Patent document 1] Japanese Patent No. 3178412 (paragraph: 0005 to 0016)    [Patent document 2] Japanese Patent Laid-Open No. 9 (1997)-31333    [Patent document 3] Japanese Patent Laid-Open No. 2001-308090    [Patent document 4] Japanese Patent Laid-Open No. 2005-45230